1. Field of the Invention
The present invention relates to a semiconductor device such as a semiconductor memory device, which can be preferably applied to circuit blocks arranged at a small pitch in the vicinity of a memory cell array.
Priority is claimed on Japanese Patent Application No. 2007-282035, filed Oct. 30, 2007, the contents of which are incorporated herein by reference.
2. Description of Related Art
In accordance with recent progress in digital techniques, portable digital apparatuses such as a cellular phone and a portable media player have been manufactured, and technical innovation has rapidly progressed. Such technical innovation for portable apparatuses includes, not only improvement in processing performance, but also in size-reduction or longer operation time of the apparatuses. Therefore, size-reduction and lower-power consumption (by voltage reduction or the like) are required for semiconductor devices installed in the portable apparatuses.
For a DRAM (dynamic random access memory), which is one of the semiconductor devices, not only size-reduction but also an increase in memory capacity is required, and thus highly integrated structures have been developed. For such highly integrated structures of DRAMs, various designs have been proposed. For example, a novel technique has been developed for the layout of bit-line pairs, which are connected to memory cells and arranged at a small pitch (see, for example, Patent Document 1: Japanese Unexamined Patent Application, First Publication No. 2007-122834).
Also for the lower-power consumption of DRAMs, various methods have been examined. DRAMs require regular memory refreshing, and slight electric current flows through the memory cells (i.e., memory elements). Therefore, the amount of data stored in the memory cells decreases as time elapses. If the amount of decrease in the stored data exceeds a specific limit, the data cannot be accurately read, that is, the data is destroyed. In order to solve this problem, sense amplifiers are driven at regular intervals, so as to perform memory refreshing in which re-amplified data is restored in the relevant memory cells. Among the operations of DRAMs, the above memory refreshing causes large power consumption, and how to decrease such power consumption has been examined for DRAMs which are used in portable apparatuses.
Here, a decrease of the operating voltage of each sense amplifier is effective for reducing the power consumption. However, the sense amplifier amplifies a very small differential potential of the relevant bit-line pair. Therefore, if the operating voltage is decreased, the operation speed may decrease, or sufficient amplification may not be performed.
In a known method for maintaining desired performance of sense amplifiers even with a low operating voltage, the threshold voltage (indicated by “Vt” in this specification) of transistors, which form each sense amplifier, is lowered. However, when the amplification of the differential potential of the relevant bit-line pair has been saturated, a leakage current flows through a CMOS (complementary metal oxide semiconductor) flip-flop, which is a major element of the relevant sense amplifier, where the lower the threshold voltage Vt the larger the leakage current. The dependence relationship between Vt and the leakage current is not linear, and a few-ten-percent difference in Vt may cause a difference of a few figures in the leakage current. Increase in the leakage current directly causes an increase in the power consumption Therefore, the method of lowering Vt easily reaches a limit, and methods using a circuit technique have been examined.
FIG. 1 of Patent Document 2 (Japanese Unexamined Patent Application First Publication No. 2001-332087, also see pages 6 to 9) shows a sense amplifier provided by a circuit technique in which a sort of the amplification circuit is added to a CMOS flip-flop so as to perform amplification, which differs from that of the CMOS flip-flop, in an initial stage of the relevant sensing (i.e., perform presensing). Below, such an additional amplification circuit is called a “presense amplifier”.
As the presense amplifier is an additional circuit, it increases the circuit area of the sense amplifier. Generally, the sense amplifier is repeatedly arranged (i.e., many sense amplifiers are arranged). Therefore, only a slight increase of each sense amplifier in the circuit area causes a large influence on the total area of the relevant semiconductor memory. Accordingly, it is preferable to provide a circuit arrangement which requires a small number of new structural elements, or a small number of necessary control signals. The presense amplifier in FIG. 1 of Patent Document 2 needs seven transistors and two control signals as dedicate elements and signals.
In addition, the presense amplifier is not an ordinary-use circuit such as a CMOS flip-flop, and a standard circuit structure thereof has not yet been established. Probably various examinations will be performed in the relevant technical field.